1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically to a setting of an operation mode such as a test mode in the semiconductor device.
2. Description of Related Art
Conventional semiconductor devices have a test mode for testing and verifying an operation of the device itself, in addition to an ordinary operation mode. To enter this test mode, it is necessary to provide a signal such as a mode switching signal from an external device. In addition, it is required that a circuit responding to the external signal to set various sections of the semiconductor device, is provided internally in the semiconductor device.
Generally, when the device is to be put into the test mode, a voltage higher than a power supply voltage is applied to a predetermined terminal, so that the high voltage is detected by a high voltage detection circuit. In response to detection of the high voltage by the high voltage detection circuit, the device is actually put into the test mode. In this case, high voltage detection circuits of the same number as that of the test modes are required. This is a hindrance to reduction of the semiconductor device chip area.
In order to overcome this disadvantage, U.S. Pat. No. 5,036,272 proposes one test mode setting circuit, which is called a "first prior art" hereinafter. The disclosure of U.S. Pat. No. 5,036,272 is incorporated by reference in its entirety into the present application. FIG. 1 shows, in a modified form, the test mode setting circuit disclosed in U.S. Pat. No. 5,036,272.
The shown test mode setting circuit of the first prior art includes a plurality of input buffers IB.sub.3-0, . . . , IB.sub.3-4, connected to a plurality of input terminals IN.sub.3-0, . . . , IN.sub.3-4, respectively, and on the basis of input signals supplied to the input buffers, a plurality of output signals OUT.sub.3-0, . . . , OUT.sub.3-16 are generated.
A high voltage detection circuit HV.sub.3-1 discriminates whether or not a high voltage is applied to the input terminal IN.sub.3-0. When the high voltage is applied, the high voltage detection circuit HV.sub.3-1 generates a high level output signal, which is supplied in common to a plurality of NAND gates NA.sub.3-1, . . . , NA.sub.3-16, so that these NAND gates NA.sub.3-1, . . . , NA.sub.3-16 are enabled. Thus, decoded signals outputted from a decoder DEC.sub.3, which has an input connected to outputs of the input buffers IB.sub.3-1, . . . , IB.sub.3-4, are passed through the NAND gates NA.sub.3-1, . . . , NA.sub.3-16, and outputted through inverters INV.sub.3-1, . . . , INV.sub.3-16 as the output signals OUT.sub.3-1, . . . , OUT.sub.3-16, which are used to set different sections of the semiconductor device.
In the shown example, the decoder DEC.sub.3 has an input of four bits, and therefore, has 16 outputs corresponding to 16 bits.
Thus, if the high voltage is applied to the input terminal IN.sub.3-0, the high voltage detection circuit HV3-1 outputs the high level signal, which is supplied to the NAND gates NA.sub.3-1, . . . , NA.sub.3-16. On the other hand, information supplied to the input terminals IN.sub.3-1, . . . , IN.sub.3-4 is decoded by the decoder DEC.sub.3, and one of the output signals OUT.sub.3-1, . . . , OUT.sub.3-16, corresponding to a desired test mode setting signal, is brought to a high level. As a result, the device is put in the test mode.
In order to minimize the number of high voltage input terminals and at the same time to be capable of setting an increased number of different test modes, U.S. Pat. No. 4,841,233 proposes one test mode setting circuit, which is called a "second prior art" hereinafter. The disclosure of U.S. Pat. No. 4,841,233 is incorporated by reference in its entirety into the present application. FIGS. 2 and 3 show, in a slightly modified form, the test mode setting circuit disclosed in U.S. Pat. No. 4,841,233.
The circuit shown in FIG. 2 includes input terminals T.sub.4-1, T.sub.4-2 and T.sub.4-3. The input terminal T.sub.4-1 is connected to an input of an input buffer IB.sub.4-1 and an output of an output buffer OB.sub.4-1. The input terminals T.sub.4-2 and T.sub.4-3 are connected to an input of input buffers IB.sub.4-2 and IB.sub.4-3, respectively.
The input terminal T.sub.4-2 is also connected to a high voltage detection circuit HV.sub.4-1, which has a output "A" connected to an control input of latches LA.sub.4-1 and LA.sub.4-2. A data input of the latches LA.sub.4-1 and LA.sub.4-2 are connected to the input terminals T.sub.4-1 and T.sub.4-3, respectively, and a data output of the latches LA.sub.4-1 and LA.sub.4-2 and the input buffer IB.sub.4-1, IB.sub.4-2 and IB.sub.4-3 are connected to an internal control circuit CIR.sub.4.
Each of the latches LA.sub.4-1 and LA.sub.4-2 is constituted of, as shown in FIG. 3, a pair of NAND circuits NA.sub.5-1 and NA.sub.5-2 connected to form a latch, and a third NAND circuit NA.sub.5-3 for bringing the latch in a set condition. If the output "A" of the high voltage detection circuit HV.sub.4-1 is brought into a logical high level "H", the NAND circuit NA.sub.5-3 is enabled, and a signal applied to an input terminal IN.sub.5-1 is held in the latch consisting of the NAND circuits NA.sub.5-1 and NA.sub.5-2. Incidentally, a terminal R.sub.5-1 is a power-on-reset terminal, so that this latch is reset in response to a power-on of an electric supply.
In the above mentioned arrangement, when the high voltage is applied to the terminal T.sub.4-2, the output "H" of the high voltage detection circuit HV.sub.4-1 is brought to a logical high level "H". At this time, if the input signal of the high level "H" is applied to each input terminal, the data output of the latches LA.sub.4-1 and LA.sub.4-2 are fixed to the high level "H". Thus, the device is put in the test mode.
However, the above mentioned conventional test mode setting circuits are disadvantageous in the following points:
In the test mode setting circuit of the first prior art, in order to enter the test mode, it is necessary not only to supply the high voltage to the input terminal IN.sub.3-0 for the high voltage input, but also to supply signals to the other input terminals IN.sub.3-1, . . . , IN.sub.3-4. In ordinary cases, there is no terminal used for only the test mode. In other words, one of the existing terminals is used as the input terminal used for setting the test mode. Accordingly, it is not possible to carry out a test which requires changing the level of the input signals supplied to the input terminals IN.sub.3-1, . . . , IN.sub.3-4.
In the test mode setting circuit of the second prior art, on the other hand, the above mentioned disadvantage of the first prior art has been solved. However, a test mode setting manner is a problem. For example, if the input signal level of the high voltage detection circuit HV.sub.4-1 is temporarily inverted or flipped in the ordinary operation due to power supply voltage noise or another adverse influence, there is a possibility that the device is erroneously put in the test mode depending on the condition of the input signals supplied to the input terminals T.sub.4-1 and T.sub.4-3. Once the device is put into the test mode, the device cannot resume the ordinary operation condition unless the power supply is shut down. Depending upon the status of the board on which the device is assembled, the device is fixed in the test mode into which the device never enters.